Equalization functions are used to compensate for frequency specific attenuation of signals that can occur when a signal is transmitted through a transmission line. The amplitude of the signal on the transmitting side is called the launch amplitude. On the receiving side of the transmission line, the amplitude of the received signal may be significantly less than the launch amplitude due to attenuation. The level of attenuation is related to the frequency of the signal passing through the transmission line as well as the length of the transmission line.
An exemplary communications system may include a transmitter, a transmission line, an equalizer circuit coupled to the receiving end of the transmission line, and a receiver. The equalizer corrects the output of the transmission line, replacing the frequencies attenuated by the transmission line and producing a signal from which the receiving chip can extract the transmitted bits. In applications with a variable length transmission line an adaptive equalizer is used. Adaptive equalizers utilize a feedback loop to compensate for changes in attenuation of the input signal due to the variable length of the transmission line. The transmission line may include a conductor, an optical fiber, a wireless link, or any other path by which signals may travel from one point to another.
A conventional adaptive equalizer system typically includes: an energy difference integrator (EDI), an inverse cable filter, a slicer, and an output driver. The term “slicer” refers to an element that delivers an output signal whose amplitude range corresponds to input-signal voltages between two predetermined limits (e.g., a clipper-limiter). The energy difference integrator compares the signal amplitude after the inverse cable filter with the signal amplitude after the slicer. The difference between those signals serves as a feedback control signal for the inverse cable filter.
FIG. 1 is a block diagram of conventional EDI 100. As shown in FIG. 1, the functions of conventional EDI 100 are usually implemented in several separate blocks (e.g., full-wave rectifiers 110-120, difference circuit 130, and integrator 140), which results in the use of more die area than is desirable. In addition, the implementation is often single-ended, which increases the sensitivity of the circuit to noise resulting in higher jitter. The term “single ended” refers to a circuit in which signals are referenced to a “common connection” in the circuit. Typically, the common connection is ground.
As shown in FIG. 1, a conventional EDI circuit may include a conventional full wave rectifier circuit. A conventional full wave rectifier circuit is described by Kimura Katsuji in a paper entitled, “Some Circuit Design techniques for Bipolar and MOS Pseudologarithmic Rectifiers Operable on Low Supply Voltage”, IEEE Trans. Circuit and Systems I, vol. 39, No. 9, September 1992, p. 771-777. FIG. 2 is a circuit diagram of conventional full-wave rectifier 200. Conventional full wave rectifier 200 is based on transistors that have different emitter areas. That is, the rectification is achieved by intentionally using different emitter areas k. For example emitter areas 202 and 204 vary from emitter areas 206 and 208 by a factor of k. The emitter degeneration is used only to increase the input dynamic range. Thus, the conventional solution teaches away from using the same emitter areas. Disadvantages of the conventional solution include that to achieve suitable rectification the factor k has to be bigger than 1, for example in a preferred embodiment of the conventional solution, the value of k is eight. This significantly limits the bandwidth of the stage making the circuit unusable for high-speed designs. It would be desirable to have an improved EDI function that uses smaller die area, is less sensitive to noise, does not limit bandwidth, and can be used at high-speed.